基于SiliconBackPlane平台的机顶盒soc设计

摘要:随着IC技术的发展,利用IP库为机顶盒芯片提供了一个完美的解决方案。单片soc相比以前的芯片组解决方案具有很多直接的优势,比如能耗和面积。该文尝试利用SiliconBackPlane 平台来设计了一种机顶盒的soc。首先,建立了机顶盒soc体系的数据流图,进行了系统划分,诸如,CPU,DSP,存储单元及其他的一些数字模块。然后,利用SiliconBackPlane平成soc的片上总线设计,以适应不同模块的通信带宽。最后,进行了简短的分析。

关键词:IP库;机顶盒soc;片上总线

中图分类号:TN492文献标识码:A文章编号:1009-3044(2010)13-3548-02

A Set-top Box Soc Design using SiliconBackPlane

CHEN Xiang-yang, ZHANG Zheng-ping

(Key Lab of Micro-electro & Software Technology, Guizhou University, Guiyang 550025, China)

Abstract: With the improvement of IC technology, IP library other than cell library provide a excellent solution for set-box soc ,one soc solution have many advantages than traditional chip set solution, such as power and area. This article tries to design a set-top box soc using Sonics SiliconBackPlane. First,constructing dataflow of the soc, partitioning the system with several necessary function blocks, such as CPU, DSP, memory, and other digital parts of the set-top-box soc. Then, in order to make every part work well, Sonics SiliconBackPlane was used as the on-chip interconnect platform to meet various parts's bandwidth. In the end, a short analysis was given.

Key words: IP library; set-box soc; on-chip interconnect

With the progress in communicating, and video and image process, the set-top box, due to soc technology, will take on the medium of multimedia and information superways in the future. The soc of set-top box shown in Fig. 1 is used as an example.

The video or audio digital signals come from the RF-module or from the hard-disk, A decryption unit is used to decrypt encrypted video streams. Then the signal can either be shown on a TV screen or saved to the hard-disk.

1 SoC design

Today’s circuits for Set Top Box applications is of high integration, Chip complexity is in the range of 8 Million synthesizable gates and 3 Mbits of embedded static RAM memory. Main clock frequency is 200MHz and circuits are organized around an internal proprietary bus. Generally, the set-top-box soc architecture design mainly focuses on embedded CPU and bus related topics like bandwidth requirement or detailed bus architecture[1].

1.1 Dataflow Analysis

A typical of a set-top-box comprises the functions: audio decoding, video decoding (e.g.MPEG2), video pixel processing, and the dataflow is designed as figure 2 below, the audio processing

chains for analog and digital remain independent, while the corresponding video-processing chains interact in a convergence to the screen, and a VCR output [2].The figure describes functional blocks, and the dataflow between blocks with their worst-case bandwidths.

1.2 Partitioning the system

the system architecture flows the conventional solution,which includes a RISC and a variety of ASIC processors, I/O components, and a SDRAM subsystem. Partitioning the system is accomplished by mapping this graph onto processors, DSP, memory, communications resources, and so on. Form dataflow above and with SilionBackplane platform, the partition is designed as below.

2 on-chip interconnect

Now, the most frequently used on-chip interconnect architecture is the shared medium arbitrated bus, where all communicating devices share the same transmission medium, such as AMBA/AHBA from ARM. The operating frequency of the shared bus depends on the propagation delay in the interconnection wires. This propagation delay, in turn, depends on the number of IP cores connected to the wires. Each core attached to the bus adds a parasitic capacitance, and therefore, the performance will degrade with system increase. One soc can consisting of tens or hundreds of IP blocks, such bus-based interconnect architectures cannot fulfill the bandwidth requirements of high-data-rate traffic[3]. With this problem, let us see a interconnect bus provide by the Sonics solution. SiliconBackplane is a quasi on-chip bus to which users attach intellectual-property blocks to create system-on-chip designs. This provides greater flexibility for the subsystem itself and the soc as a whole[4-5]. So, it makes it easy to accomplish complex soc design. Multiple subsystems, each with an independent clock frequency and data path width, can be connected in tree or fully connected topologies to isolate local data flows, improving total system bandwidth while reducing soc area and power consumption. Runs over 20,000 clock cycles, with fixed priority, figure 4 shows that ,the CPU absorbs almost all spare bandwidth and the GPH gets no bandwidth for a long period. This simulation below illustrates the disadvantages .

However, the SiliconBackplane platform can almost meet the bandwidth demand as is show as figure 5[6].

3 Conclusions

Using SiliconBackplane platform can meet requirement of the every part’ bandwidths of the design, using the model, every part on the soc can communicate well. Also ,it simplify the entire design .With the complex of the soc increase, calling for still higher levels of integration,network on chip(NOC)already have been put forward ,the SiliconBackplane maybe give a conceptional method.

4 Acknowledgments

Thank the key lab of micro-electro & software technology in Guizhou University and Opencore website which provides EDA tools and many useful RTL code. The topic is assisted by Scientific and technological project fund of Guizhou University. The project Number is Z083152.

References:

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