A Programmable Logic Controller Timer System based on Parallel Operation

Abstract: According to the work principle of small PLC, the timer operation instruction, this paper puts forward a parallel algorithm using the FPGA design a small PLC timing system, describes the design principle of the timer system, and the simulation of the system design vivificates timer and its function. The design and manufacture process of users in program execution module programmable logic controller (PLC) in RAM memory unit operation, not the timer, it with only a few execution time programmable logic controller (PLC) of user programs.

Key words: PLC; FPGA; parallel operation

1 Introduction

The timer is an important soft-devices programmable logic controller (PLC) [1] [2], and on the basis of time relay control system can be used as the relay. The timer is widely used in automatic control system, such as sampling time, regularly check, timing scan, etc, is to achieve timing time come programmable hardware, software regularly and programmable hardware of this time. Programmable logic controller (PLC) provide hundreds of thousands of timer [3] [4], and their timing unit usually has three like a ms, 10 ms and 100 milliseconds. If the timer to realize all by hardware design, it would be relatively simple, but take up a lot of hardware resources. Therefore, it has great practical significance, such this large number of timer function is reasonable. This paper puts forward a kind of using the FPGA parallel algorithm theory, design a kind of small PLC timing system. The timer system by the clock generator, time unit, timing control unit, the chip choose circuit. Several memory cells form a timing device. In the speed of operation time 1 lady pulse, timer control module of the judges of the dynamic information encoding state three time unit, operation time process. At the same time, the timer control module will scan the user program implementation status module operation timer, let the user program execution module operation RAM memory cell of the timer itself, and not just took a little time for the execution of the programmable controller of user programs. This paper introduces the theory and structure of the system, the state transition FPGA timer control module of the graph, the user program execution timing diagram of module run in the timer, finally take a experiment, and gives the analysis results.

2 SYSTEM DESIGN

To different types of digital programmable logic controller (PLC) timer is different, neither type of timer. Small PLC timer has three working state. The first state is when the input conditions are not satisfied, software component in power-down the country and the corresponding coil timer the contact is disconnected. The second is the state when the input conditions satisfied, timer working status and the corresponding contact is disconnected. The third state is when time is completed, the input conditions are still satisfied and the corresponding contact is closed. The PLC timer timing value T = timing resolution factor multiple timing constant K. In programming applications, once the timer is selected, the timing resolution factor is subsequently identified as 1 ms, 10ms or l00ms. Figure 1 is a ladder program diagram of timer T0. Timer T0 is one soft component which made up of coil and its status is "1" when power is on and "0"when power is off. When timing is completed, the soft component of timer T0 is power on, its contact closes and its status becomes "1 ", when timing is not completed, the soft component of timer T0 is power off, its contact breaks and its status stays "0". If the timing resolution factor of T0 is 100ms and K is 100 then the time value T = 100ms x 100 = 10s.

An example of the timing process is shown in Figure 1.

When the input signal X0 is connected, the coil of timer T0 is driven. The timer counts the 100ms pulses, at the same time, the counting value is continually compared with the preset value. When these two values are equal, the contact of T0 will be connected. The function is, once the timing coils is power on, its contacts will be closed after l0s time-delay. When the input signal X0 is disconnected, the coil will be reset and power off, the counter value and the output of contact T0 will both be reset immediately.

In order to transfer one timer data between the PLC user program execution module and timer in one time, a 32-bit data line is adopted, shown in Figure 2. the operations of User program execution module on timer are OUT Txxx, Kxxx, and the corresponding state of timer's input conditions. Txxx is the address, Kxxx is the timing data. Then the information that PLC user program execution module exports to the timer system mainly contain the timing data, the timing address, the status of soft coil and the flag status of timer(being used or not). The information that the timer system exports to PLC user program execution module mainly contain the timing address, the completing status of the process of timing, the control information of message read or written, etc.

Timer unit is independently addressed through the address bus and chip select signals, and processes the timing operation on selected unit address. By mapping the addresses, the timer number and the unit address are one-one correspondent. The directly mapped addresses while compiling the instructions are shown in Table I.

According to the operational principle of timer, the timer system based on FPGA is designed to consists of four modules, that are clock generator unit, timing unit, timing control unit and chip select circuit [5]. The block diagram of timer system is shown in Figure 2.

The clock generator unit generates required reference clock cycle 1ms. clkin is the input signal from the main clock that generated by the 50MHz system frequency; clk_lms is the 1 ms periodic signal output. At each rising edge, it will trigger one counting operation on timer unit by the timer control unit.

Timing control unit (Timer controller) is the core component of the whole timer design. Its main function are detecting the usage status of timer i, and the operation status of timer i and the completing status of timing. If the timer i is in process and the timing hasn't completed, this timer will be minus by 1.

When timing completed for the first time, the information that closing the contact is sent to the soft component area of corresponding position. When timing completed for the 2nd and even the Nth time, the information won't be sent to the soft component area of corresponding Bit processing storage unit. When timer is power off for the first time, the information that breaking the contact is sent to the soft component area of corresponding Bit processing storage unit. When timer is power off for the 2nd and even the Nth time, the information won't be sent to the soft component area of corresponding position.

Timing control unit does not involve the operation of instruction decoding. The timer unit carries out the cycle counting in the 1ms reference clock after the timer unit has been given an initial value. Timing control unit processes state transitions in accordance with the clkin frequency. In other words, timing control unit samples I ms reference clock and complete the counting operation of the 1ms reference clock. During the initialization process, timing control unit starts the counting operation according to the timer _en signal from the host controller. During the decoding process, timing control unit pauses the counting operation according to timer_reg signal from the host controller, and give the operating right of timer unit to the host controller, till completes the decoding of the host controller.

Timing unit (Timer) is actually a 256 bytes length, 32 bits read/write RAM section with a read/write independent dual data bus. There are three kinds of PLC timer: 1ms, l0ms and l00ms. Assign a 32-bit length of the memory cells for each timer, the definitions of each unit are as follows:

D31: Using flag bit. 1 indicates that the timer will be used in the program and 0 indicates that it won't use the timer. The flag bit is identified in the initialization module;

D30: input status bit. 1 indicates that the timer is power off, 0 indicates that the timer is power of f;

D29: output status bit. 1 it indicates that the timing time of timer has reached, and the timer has output, and 0 indicates that the timing time of timer hasn't reached, it is counting and timing and the timer has no output

D28: reservation

D27~ DO: the initial value of timer, which acts minus subtraction. The subtraction is set in the timing control unit. The timing unit processes counting function of timer, completes the timer's clocking function under the coordination and control of control unit. Host controller unit (Host controller) is the execution module of PLC user program, where all user programs are compiled and executed. During the execution process of the "out txx kxx" instruction, host controller unit completes the start and stop control of timer unit, and exports the timer's contact state by the operation of corresponding flag bit. The timer chip select circuit is composed of combinational logic circuit by the XOR circuit. It ensures the main controller unit and the timing control unit will not occur access violation when they are accessing timer unit. These two controllers have respective chip select signals and enable signals, cooperating with the timing unit address, can access timing unit.

3 FUNCTIONAL SIMULATION

According to the timer logic design mentioned above, take five units of the timer OOH ~04H. From the first address, the different address of timer ram are written into the same number as the initial value. From the first address again, follow three steps: read, minus 1 count and write to complete the minus 1 count operation of the unified unit timer and then the address plus 1. Finally, repeat the above three steps until complete the timing minus 1 operation of initial unit. In the three steps discussed above, the following time need to add to the timer _req signal simulation and the continuous counting function simulation of t_clkl ms. The functional simulation of 1 ms timer unit is shown in Figure 3.

First 80ns, write the initial value 0000000fH into timer Jam unit 0H~04H. From the 80ns to the 110ns, complete the minus 1 count operation of timer unit 00H following the three steps of state 2,3,4; from the 160ns to the 190ns, add the timer_req high level effective signal, at this moment, the minus 1 count function suspends at unit02, the address bus and data bus outputs high impedance state; after 110ns, the timer Jeq recovers low level, then complete the minus 1 count operation of 03H and 04H; from the 280ns to the 310ns, set the t_clk 1 ms signal as low level, then the address and data buses are high impedance state; after the 3l0ns, continue minus 1 and counting functions; from the 310ns to the 380ns, rewrite the initial value because of this is a cycle simulation. But the actual situation is that the initial value writing operation should be completed by the host controller in the initialization process. It is only for convenience to perform cycle simulation here. The continuous minus 1 operation after 380ns meet the functional requirements.

4 CONCLUSION

In short, design to the design of the expected demand function. Small modifying hardware design has become just as easily modify the software design, and shorten the design cycle of the design, make the timer debugging easier. The most important is, this design enhances the reliability of the system, and meet the needs of the current complex automatic control system.

References

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